Modern electronic testing systems perform certain electronic circuit tests at the designed operational speed of the device under test (DUT). But performing structural tests of electronic devices at operation speed can introduce many problems. One primary problem is increased power consumption during switching. This increased power consumption experienced during operational speed testing can often be much higher than the power consumption experienced during the DUT's normal operation. As such, the increased power consumption can affect test results, causing the device under test to fail, or appear to fail. For example, in some fault tests, increased switching power consumption during scan capture can degrade performance to the point of test failure. Additionally, in all fault tests, the increased power consumption during switching can aggravate IR-drop and crosstalk, which can also manifest as a failed test. Worse, increased power consumption can cause faults, introducing stress-related failures in the device under test.
In order to address this problem, industry has developed testing methods that attempt to reduce power consumption during the testing process. Many conventional methods restrict the test application to only those portions of the DUT that are currently being tested. The logic operators and other portions of the DUT that are not being tested are assigned a random bit as a place holder during the testing process. These logic operators are called non-determinative operators and often notated as “do not care” or don't-care bits.
Conventional systems randomly fill don't-care with either a zero or a one. The typical random fill method can provide a slight increase in fault coverage by detecting faults not explicitly targeted during a test, sometimes referred to as “fortuitous detection.” Industry studies have shown fortuitous detection coverage to be very similar to randomly filled don't-care values, which is relatively high for the first few patterns. However, the coverage provided by fortuitous detection drops very quickly with subsequent patterns.
Further, randomly filling the don't-care bits can also introduce power related problems. For example, randomly filling the don't-care bits can cause an increased number of transitions during scan-in, relative to simply filling in the don't-care bits with all zeros. The increase number of transitions can, in turn, cause high power dissipation. The increased power dissipation during scan-in can be mitigated somewhat by lowering the test frequency, but lowering the test frequency increases the total time necessary to conduct the test. Worse, often 80% or more of the data bits in the scan chain being shifted into the chip are don't-care values, which magnifies the problems caused by randomly filling the “don't' care” bits.
Industry has developed several heuristic methods to select the fill value for don't-care bits. One modern heuristic method assigns all don't-care bits a value of zero, called the “tie to zero” method. Another modern method assigns all don't-care bits a value of one, called the “tie to one” method. The “thousand fill” method fills the don't-care bits of the first 1,000 post compaction results with all zeros, and fills the don't-care bits of the next 1,000 patterns with all ones, repeating the alternation in blocks of 1,000 for the remainder of the test patterns. The “random chain” method randomly selects half of the scan chains, filling the don't-care bits in the selected chains with all ones, and filling the don't-care bits in the rest of the chains randomly.
The “fill adjacent” method uses information about the care bits to fill in values of the don't-care bits on a care bit by care bit basis. Specifically, the fill adjacent method fills don't-care bits with the most recent care bit value until another care bit is reached, after which the new care bit value is applied. The “minimum-transition fill” method uses a process similar to that of the “fill adjacent” method, and includes aspects to reduce transitions in the test vector. The “random four adjacent” method randomly selects four chains, filling the don't-care bits of the selected chains according to the fill adjacent method, and fills the don't-care bits in the remaining patterns randomly.
As shown, current heuristic methods for modern electronic testing systems try to reduce overall switching power by reducing the overall average power. Most systems use a general method for determining all don't-care values. But a general method, applied to all devices under test, does not take into account actual circuit topology to reduce power, largely because current heuristics cannot efficiently process actual circuit topography. These conventional methods look only at specific simple heuristics to attempt to reduce the power on an average basis, across many different devices. As such, typical methods to reduce average power fail to achieve the power reduction possible if actual circuit topography were considered.
Therefore, there is a need for a system and/or method for power reduction in at-speed circuit testing that addresses at least some of the problems and disadvantages associated with conventional systems and methods.